Prof. Mark B. Josephs

BSc (Lond), MSc (Oxon), DPhil (Oxon), FBCS CITP, Senior Member of the IEEE, Member of the UKCRC

I am a professor of computing within the Department of Informatics, Faculty of Business, London South Bank University. I am currently Director of the Institute for Computing Research. This incorporates the Centre for Concurrent Systems and Very Large Scale Integration that I founded in 1993.

The best way to contact me is by email: Mark.Josephs[AT]lsbu.ac.uk or, internally, josephmb[AT]lsbu.ac.uk. N.B. (Replace [AT] by @.)
Voicemail: +44 20 78157413
FAX: +44 20 78157793
My postal address is Prof MB Josephs, Faculty of Business, London South Bank University, 103 Borough Rd, London SE1 0AA, UK.

You will find my full curriculum vitae here.

Teaching

• a linked pair of second year undergraduate modules on operating systems (last revised 2004/5);
• another second year undergraduate module on computer architecture (last revised 1998/9);
• a third year undergraduate module on Communicating Sequential Processes (last revised 1998/9).

Research

I began investigating asynchronous process calculi (as variations on Theoretical CSP) as long ago as 1988, initially in collaboration with Tony Hoare and He Jifeng at the Programming Research Group, Oxford, and subsequently in collaboration with Jan Tijmen Udding (University of Groningen, and Washington University, St Louis) and Tom Verhoeff (Eindhoven University of Technology). The results formed part of Oxford's contribution to ESPRIT Basic Research Action 3006 CONCUR (Theories of Concurrency: Unification and Extension), 1989-1992, and were first reported in three technical reports:

• A Theory of Asynchronous Processes (PRG-TR-6-89), co-authored by Tony and Jifeng. This theory of nondeterministic data-flow networks consisted of a mathematical model and a process algebra. The report was widely distributed and followed up by a paper at an IFIP WG 2.2/2.3 Working Conference in 1990.
• An Algebra for Delay-Insensitive Circuits (WUCS-89-54), co-authored by Jan Tijmen. This process algebra was applied to a number of small case studies: Alain's D and Q elements (CAV'90); a stack (DCC'90); non-blocking arbiters (CONCUR'90).
• Receptive Process Theory (TUE CS Note 90/8), subsequently published in Acta Informatica, Volume 29, Number 1, 1992, Pages 17-31. This theory consisted of a mathematical model (generalising that of PRG-TR-6-89 above) and a process algebra suitable for modelling and verifying speed-independent circuits (as considered by David Dill in his PhD thesis). It is probably best known from Vijay Saraswat, Martin Rinard, and Prakash Panangaden's POPL'91 paper on the "Semantic foundations of concurrent constraint programming" in which they state that they had followed closely my treatment of receptive processes.

• Mark B. Josephs and Hemangee K. Kapoor (2007) Controllable Delay-Insensitive Processes, Fundamenta Informaticae 78(1):101-130. Preprint; Published Article.
• Hemangee K. Kapoor, Mark B. Josephs and Dennis P. Furey (2006) Verification and Implementation of Delay-Insensitive Processes in Restrictive Environments, Fundamenta Informaticae 70(1-2):21-48. Preprint; Published Article.
• Mark B. Josephs (2005) Models for Data-Flow Sequential Processes, Lecture Notes in Computer Science, Volume 3525, Pages 85-97. Preprint; Published Article.
• Hemangee K. Kapoor and Mark B. Josephs (2004) Modelling and verification of delay-insensitive circuits using CCS and the Concurrency Workbench, Information Processing Letters 89(6):293-296. Preprint; Published Article.
• Mark B. Josephs and Dennis P. Furey (2002) A Programming Approach to the Design of Asynchronous Logic Blocks, Lecture Notes in Computer Science, Volume 2549, Pages 34-60. Preprint; Published Article.