Centre for Concurrent Systems and Very Large Scale Integration
Contents
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Introduction
The CCSV is now part of the
Institute for Computing Research,
Faculty of Business, Computing and Information Management,
London South Bank University. Since its inception in 1993, the main focus of the centre has been on research into asynchronous circuit design. In the period 2000-2003, the activities of the CCSV were closely co-ordinated with those of the Centre for Applied Formal Methods. A strategic research direction for the CCSV is the development and use of computer-aided verification and synthesis tools, particularly their application to real-world design problems.
Meetings
The Institute for Computing Research advertises
forthcoming events, including research seminars and maintains a list of past events.
The following international workshop marked the launch of the Institute:
The CCSV has previously hosted the following events:
Follow this link for details of seminars, 2001-2005.
The following CCSV seminars took place in 2000:
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11 December, "Operational Semantics of Verilog",
Jonathan Bowen
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4 December, "Computing in Space and Time",
Toomas Plaks
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27 November, "Clifford Algebra",
Jon Selig
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20 November "A semantics of Verilog using Duration Calculus",
Zhu Huibiao
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13 November, "An Asymptotic Model for Clipping Line Segments",
Frank Devai
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6 November, "Hazard-free FSM Implementation in CMOS Technology",
Igors Lemberskis
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30 October, "Making routing decisions in output-buffering packet switch
design: asynchronous logic versus synchronous logic", Jun Xu
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23 October, "Petri Net Transformation", Dennis Furey
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16 October, "Self-timed FSM Synthesis", Mark Josephs
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19 January, "Can you measure the quality of digital designs?", Dave Protheroe
The following CCSV seminars took place in 1999:
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15 December, "Output buffer switch design", Jun Xu
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13 May, "Queuing Theory", Jon Warwick
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7 May, "Fred, the asynchronous processor", Erik Brunvand (U. Utah)
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30 April, "Macro1 & Mini1 -- Switch Design for Networks", Jun Xu
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25 January, "Asynchronous Huffman decoder, for compressed code embedded
processors", Steve Nowick (Columbia U.)
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14 January, discussion of the paper "Modeling and Comparing CMOS Implementations
of the C-Element"
The following CCSV seminars took place in 1998:
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10 December, "Self-Timed FSM Synthesis", Mark Josephs
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3 December, "The Network for Multicomputers --- Deadlock-freedom &
Latency", Jun Xu
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26 November, "Effect of architectural choices on compiler and OS design,
and vice versa", Francesco Pessolano
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19 November, "Hashim's Nested Code Construction", Sylvia Jennings
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12 November, "Synchrony & Asynchrony in Concurrent Systems", Martin
Bush
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5 November, "Modeling Petri Nets using VHDL - Simulation and Synthesis",
Dave Protheroe
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29 October, "Performance Estimation of Parallel DBMS through Analytical
Modelling", Kevin Lu
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22 October, "A virtual machine model for parallel acyclic graph reduction",
Dennis Furey
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15 October, "Formal Derivation of a Loadable Asynchronous Counter", Mark
Josephs
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2 October, "A low-power, high-speed stack controller designed using asynchronous
circuit techniques", Francesco Pessolano
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4 June, "Convexity, measures and lattices", Audrey Curnock
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21 May, "What reconfigurable computing has to offer", Neil Hepworth
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14 May, "Automated synthesis of dataflow networks using a functional language",
Dennis Furey
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7 May, "Introduction the SDL and MSC notations used in the telecommunications
industry", Martin Bush
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26 March, "Survey of asynchronous microprocessors", Francesco Pessolano
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12 March, "Review of a paper on neural networks", Bernard Chalk
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26 February, "Tracing the behaviour of reactive systems", Mark Josephs
Courses
The Head of the CCSV has developed the following courses:
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Operating
Systems (1999-2005) covers scheduling, storage, I/O and networks,
with exercises in concurrent programming and network programming in C and Java.
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Concurrent
Systems (1996-99) introduces a formal approach to the analysis of concurrent
systems.
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Microprocessor
Technology (1996-99) introduces the quantitative approach to Computer
Architecture, including design trade-offs concerning Instruction Sets,
Pipelined Processors and Caches.
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Asynchronous Systems
and Circuits (Oxford University, 1993-95) explores how asynchronous
systems can be designed so as to exploit the fine-grained concurrency available
in VLSI.
Projects
The CCSV has held three grants from the UK Engineering and Physical
Sciences Research Council and four contracts with the European Commission
under its Third, Fourth and Fifth Framework Programmes:
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The EPSRC, under grant reference EP/050529, supported scientific exchange and research collaboration with Caltech and NASA/JPL.
During the Summer/Autumn 2005, Josephs met Gerard Holzmann (NASA/JPL) at the SPIN model-checking international workshop and made several short visits to the Caltech Computer Science Department. He gave a departmental seminar and organized an inter-group workshop involving Alain Martin, Mani Chandy, Gerard Holzmann, Jason Hickey and John Doyle. Naderi spent two months visiting Martin's group and Nystroem from that group visited us briefly back in London. During the Winter 2006, Furey spent two months visiting Hickey's group, gave two departmental seminars and learnt about model-checking from Holzmann.
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The EPSRC, under grant reference GR/S47151, supported our participation in a European System-on-Chip consortium. Josephs led the thematic area of System Timing.
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The EPSRC, under grant reference M51567, funded the project "Translation from Delay-Insensitive Algebra into
Petri Nets, with Application to Asynchronous Circuit Design". The objectives of this project were
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To develop and to demonstrate a tool that can contribute to the computer-aided
engineering of asynchronous circuits.
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To promote a better understanding of process-algebraic specification of
delay-insensitive systems by providing a link to Petri nets.
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The European Commission contracted with us to support ACiD-WG
("Working Group on Asynchronous Circuit Design") under FP5 Microelectronics
contract number IST-1999-29119. Membership comprised 21 organisations from nine Member States and two Associated
States of the European Union. Four workshops and two schools were organised and ACiD-WG sponsored
the Eighth and Tenth International Symposia on Asynchronous Circuits and Systems
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The European Commission contracted with us to support ACiD-WG under FP4 Technologies for Components and Subsystems
contract number EP21949.
Membership comprised ten organisations from six Member States of the European
Union. Four workshops and a summer school were organised and ACiD-WG sponsored
the Third, Fifth and Sixth International Symposia on Advanced Research
in Asynchronous Circuits and Systems.
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The European Commission contracted with us to support ACiD-WG under FP3 Basic Research contract number EP7225.
Membership comprised twelve organisations from five Member States of the European
Union. Five workshops were organised and ACiD-WG sponsored the Second Working
Conference on Asynchronous Design Methodologies, hosted by the CCSV.
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The European Commission supported the EXACT ("EXploitation
of Asynchronous Circuit Technologies") project under FP3 Open Microprocessor
systems Initiative contract number 6143. The project was led by Philips Research and the CCSV was an associate partner to Manchester University. The main demonstrator of the project
was a low-power version of the decoder chip for Philips' Digital Compact
Cassette (DCC) system.
PhD Theses
The following PhD theses by CCSV research scholars are available on-line:
Technical Reports
The following CCSV Technical Reports are available:
- 2005: Using SPIN to add value to asynchronous hardware design flows. Naderi, M., Josephs, M.B.
- SBU-CISM-02-20: Automated Transformation of Delay-Insensitive Sequential Processes. Kapoor, H.K., Josephs, M.B.
- SBU-CISM-02-18: Asynchronous interconnection and
interfacing of Intellectual Property
cores in the design of Systems-on-Chip. Xu, J.
- SBU-CISM-01-21: A programming approach to the design of asynchronous logic blocks. Josephs, M.B., Furey, D.P.
- SBU-CISM-01-18: Classification and composition of deterministic processes. Josephs, M.B.
- SBU-CISM-01-17: From programs to Petri nets (to asynchronous logic). Josephs, M.B., Furey, D.P.
- SBU-CISM-01-11: Models for Data Flow Sequential Processes. Josephs, M.B.
- SBU-CISM-00-32: Heterogeneous Clustered Processors: Organization and Design. Pessolano, F.
- SBU-CISM-00-26: Asynchronous versus synchronous control logic for
interleaved memory in output-buffering packet-switch design. Xu, J.
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SBU-CISM-00-14: Asynchronous First-In First-Out Queues. Pessolano,
F., Kessels, J.
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SBU-CISM-99-21: Evaluating Heterogeneous Clustered Processors. Pessolano,
F., Josephs, M.B.
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SBU-CISM-99-10: The Use of Avalanche Multiplication in Modern Computing
and Recognition Systems: Electronic and Electrolytic. Neville, R.S.,
Neville, P.D.
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SBU-CISM-99-09:
A Critique of Some Simple Logic Operations with a Semi-insulator.
Neville, R.S., Neville, P.D.
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SBU-CISM-99-08: The Asynchronous Solid-State Avalanche Switch. Neville,
R.S., Neville, P.D.
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SBU-CISM-99-07:
An Electrostatic Approach to Transistor Equivalent Circuits. Neville,
R.S., Neville, P.D.
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SBU-CISM-99-05: RAM-Nets Modus Operandi. Neville, R.S.
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SBU-EEIE-98:
Petri net modelling and implementation using VHDL. Protheroe, D.
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SBU-CISM-98-12:
A Class of Nested Linear Block Codes and Their Decoding Algorithm.
Hashim, A., Jennings, S.M.
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SBU-CISM-98-10:
Translation of DI-Algebra to Petri Nets. Furey, D.P., Josephs, M.B.
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SBU-CISM-98-05:
Modeling and Design of Asynchronous Circuits. Josephs, M.B., Nowick,
S.M., van Berkel, C.H.
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SBU-CISM-98-03:
Co-Operative Software and Hardware Interfaces in Asynchronous Computer
Architectures. Pessolano, F.
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SBU-CISM-98-01:
The TAA machine: a statically-scheduled asynchronous clustered architecture.
Pessolano, F.
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SBU-CISM-97-10:
A solution to Object Code Incompatibility for static scheduled architectures
and its extension to Multi-ISA. Pessolano, F.
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SBU-CISM-97-09:
Comparison of the VLSI cost/performance properties of two Reed-Solomon
Decoding Algorithms. Jennings, S.M., Kessels, J.
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SBU-CISM-97-08:
A novel low-power high-performance stack controller design. Josephs,
M.B., Pessolano, F.
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SBU-CISM-97-07:
A few suggestions on how to implement self-timed finite-state machines.
Josephs, M.B.
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SBU-CISM-97-05:
A low-power, high-speed stack controller designed using asynchronous
circuit techniques. Josephs, M.B., Pessolano, F.
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SBU-CISM-97-04:
A Generalization of the Decision-Wait Element. Josephs, M.B.
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SBU-CISM-97-02:
Concepts and Notations for Concurrent System Modelling. Bush, M.E.
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SBU-CISM-96-20:
A generalization of the Decision-Wait element and its application to
the design of packet switches and stacks. Josephs, M.B.
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SBU-CISM-96-18:
Formal derivation of a loadable asynchronous counter. Josephs, M.B.
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SBU-CISM-96-05:
Behavioural modelling of asynchronous circuits. Bush, M.E., Josephs,
M.B.
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SBU-CISM-96-04:
Design disciplines and correctness calculi for asynchronous circuits.
Josephs, M.B.
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SBU-CISM-95-26:
Beyond Berlekamp-Massey. Fitzpatrick, P., Jennings, S.M.
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SBU-CISM-95-20:
From B to SPARK (An Extension to a Formal Design Environment). Storey,
A.C. (PhD thesis, supervised by CCSV and CSSE staff)
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SBU-CISM-95-14:
The Limitations to Speed-Independence in Asynchronous Circuits.
Bush, M.E., Josephs, M.B.
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SBU-CISM-95-06:
Tangram Peephole Optimizer using EDIF. Morton, S.V.
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SBU-CISM-95-03:
Designing Correct and Robust Hardware: The Case for Formal Methods and
Asynchronous Circuits. Bush, M.E., Josephs, M.B.
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SBU-CISM-95-02:
A Fast, Low Power, 32x32 bit Register Array. Morton, S.V.
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SBU-CISM-95-01:
CMOS Design of the Tree Arbiter Element. Josephs, M.B., Yantchev,
J.T.
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SBU-CISM-94-12:
Design of sequencer circuits: a case study in SI-Algebra. Josephs,
M.B., Bailey, A.M.
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SBU-CISM-94-10:
A formal description of the OMG's Core Object Model and the meaning
of compatible extension. Houston, I.S.C., Josephs, M.B.
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SBU-CISM-94-08:
A Grobner Basis View of the Welch-Berlekamp Algorithm for Reed-Solomon
Codes. Jennings, S.M.
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SBU-CISM-94-07:
Low Latency Asynchronous FIFO Buffers. Yantchev, J.T., Huang, C.G.,
Josephs, M.B., Nedelchev, I.M.
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SBU-CISM-94-06:
Formal Design of an Asynchronous DSP Counterflow Pipeline: A Case Study
in Handshake Algebra. Josephs, M.B., Lucassen, P.G., Udding, J.T.,
Verhoeff, T.
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SBU-CISM-94-04:
A Survey of Decoding Algorithms for Reed-Solomon Codes. Jennings,
S.M.
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SBU-CISM-94-02:
CMOS Design of Arbiter Circuits. Josephs, M.B., Yantchev, J.T.
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SBU-CISM-94-01:
Specifying distributed CICS in Z: Accessing local and remote resources
Houston, I.S.C., Josephs, M.B.
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SBU-CISM-93-01:
Handshake Algebra. Josephs, M.B., Udding, J.T., Yantchev, J.T.
Trip Reports
*Trip supported by ACiD-WG.
Members and Affiliates
(Standing: Bernard, Martin, Sylvia, Dennis; sitting: Jun, Mark, Francesco)
Prof.
MB Josephs, Head of Centre
Dr. ME Bush, Member
Mr. BS Chalk, Affiliate
Dr. DP Furey, Senior Research Fellow
Dr. SM Jennings, Affiliate
Dr. D Protheroe, Member
Former Members and Affiliates
Mr. SPM Hall, Research Assistant (Jun 01 - Sep 02).
Dr. HK Kapoor, Research Scholar (Sep 01 - Sep 04); currently: Visiting Assistant Professor, Indian Institute of Technology Guwahati, India.
Prof. I Lemberski, Research Fellow (Oct 00 - Sep 02);
currently: Professor, Kwangju Institute for Science and Technology, Republic of Korea.
Dr. SV Morton, Visiting Fellow (Oct 94 - Jun 95) from University of Adelaide, Australia; currently, Staff Engineer, Icera Semiconductor, UK.
Mr. Mohsen Naderi, Research Scholar (Jan 05 - Apr 06); currently: Assistant Vice President, Merrill Lynch, UK.
Dr. RS Neville, Affiliate (Feb 99 - Jun 00); currently: Lecturer, School of Informatics,
University of Manchester, UK.
Dr. F Pessolano, Research Scholar (Apr 97 - Mar 00), Research Fellow (Apr 00 - Jun 00); currently: Innovation Manager at NXP Semiconductors, The Netherlands.
Prof. JT Udding,
Visiting Fellow (Oct 93) from University of Groningen, The Netherlands; currently: Corporate Director of ICT, Frans Maase (a
leading European logistics service provider) and (part-time) Professor of Systems Engineering,
Department of Mechanical Engineering, Eindhoven University of Technology, The Netherlands.
Dr. J Xu, Research Scholar (Oct 98 - Apr 02); currently: Leading Design Engineer, Imagination Technologies, UK.
Prof. JT Yantchev, Visiting Fellow (Jan - Jun 94); currently: General Manager, Australia System on Chip Technology Centre, Freescale Semiconductor, and (adjunct) Professor, School of Computer Science, University of Adelaide, Australia.
Last altered 2nd July 2007