Programme
Monday 28th of June 2004:
08:45 Registration
09:15 Welcome by Juha Plosila
09:30-10:00 Session 1: Invited talk from Nokia Research Center (Chair: Juha Plosila)
- J. Liimatainen
"Asynchronous IC technology research in Nokia"
(abstract)
10:00-11:00 Session 2: GALS I (Chair: Eckhard Grass)
- T. Kapchitz and R. Ginosar
"Using model checking for synchronizer verification"
(abstract)(slides)
- F.K. Gürkaynak, S. Oetiker, N. Felber, H. Kaeslin and W. Fichtner
"Is there hope for GALS in the future?"
(abstract)(slides)
11:00-11:30 Coffee Break
11:30-13:00 Session 3: Energy, Noise and Design-for-Test (Chair: Ad Peeters)
- E. Ou and M. Nystrom
"Energy-delay trade-offs involving voltage scaling in synchronous and asynchronous systems"
(abstract)(slides)
- P. Liljeberg, J. Tuominen, S. Tuuna, J. Plosila, and J. Isoaho
"Self-timed approach for noise reduction in SoC"
(abstract)(slides)
- A. Efthymiou, J. Bainbridge and D. Edwards
"Remedy for an asynchronous weakness: a fully-testable interconnect fabric"
(abstract)(slides)
13:00-14:00 Lunch
14:00-16:00 Session 4: Asynchronous Logic Synthesis (Chair: Jens Sparsø)
- J. Cortadella and A. Yakovlev
"Ten Years of Petrifying: where are we now?" (Invited talk)
(abstract)(slides)
- H.K. Kapoor and M.B. Josephs
"Decomposing specifications to resolve state coding conflicts in asynchronous logic synthesis"
(abstract)(slides)
- J. Carmona and J. Cortadella
"ILP models for the synthesis of asynchronous control circuits"
(abstract(slides)
- I. Lemberski and K. Kim
"Model of multi-level delay-insensitive logic implementation with intermediate signaling"
(abstract)(slides)
16:00-16:30 Coffee Break
16:30-17:45 Session 5: SWOT Analysis (Chair: Marc Renaudin)
- Discussion within groups (16:30-17:15)
- Meeting Design Constraints (Leader: Ran Ginosar)
- System Integration (Leader: Frank Gurkaynak)
- Design Automation (Leader: Jens Sparsø)
- Presentation by group leaders (17:15-17:45)
(slides)
19:00-23:00 Dinner at the Hotel Airisto Strand
Tuesday 29th of June 2004:
09:00-11:00 Session 6: On-Line Testing and Self-Timed Circuits (Chair: Ran Ginosar)
- P.D. Hyde and G. Russell
"Scheme for on-line error detection in aynchronous systems"
(abstract)(slides)
- A. Bystrov, D. Koppad, A. Yakovlev
"On-line testing of asynchronous circuits"
(abstract)(slides)
- C. Brej
"Safe early output: an improved QDI logic system"
(abstract)(slides)
- A. Yakovlev, A. Bystrov, D. Sokolov, J. Murphy, V. Varshavsky and V. Marakhovsky
"Phase-difference based logic: principle and applications"
(abstract)(slides)
11:00-11:30 Coffee Break
11:30-12:30 Session 7: GALS II (Chair: Juha Plosila)
- M. Krstic and E. Grass
"GALS baseband processor for WLAN"
(abstract)(slides)
- S. Fairbanks and S. Moore
"Asynchronous or synchronous: a misleading choice?"
(abstract)(slides)
12:30-12:45 Presentation of Updated Reports and Closing Remarks by Mark Josephs
12:45-14:00 Lunch
14:00-15:00 Closed Session: ACiD-WG Technical Management Committee Meeting
