ERSA'05 CONFERENCE SCHEDULE The 2005 International Conference on Engineering of Reconfigurable Systems and Algorithms Monte Carlo Resort, Las Vegas, Nevada, June 27-30, 2005 Note: There are a number of other sessions (not listed as part of ERSA'05 schedule) that are of significant interest to ERSA conference participants (sessions belonging to other joint conferences in this event.) Therefore, you are encouraged to also check the schedules for other joint conferences. In particular, some sessions in PDPTA'05 and CDES'05, discuss topics that are within the scope of ERSA; these have been scheduled so that ERSA attendees can also participate in them. =================================================================== June 26 June 26 June 26 June 26 June 26 June 26 June 26 June 26 =================================================================== 03:00 - 09:00pm: REGISTRATION (Second Floor, Conference Lobby; 1-5) =================================================================== June 27 June 27 June 27 June 27 June 27 June 27 June 27 June 27 =================================================================== 6:30am - 5:00pm: Registration (Second Floor, Conference Lobby: 1-5) 08:30 - 08:45am: The 2005 International MultiConference in Computer Science and Computer Engineering - Opening Remarks Hamid R. Arabnia (General Chair, IMCSE'05) University of Georgia, Georgia, USA (LOCATION: Lance Burton Theater) 08:45 - 09:45am: Keynote Lecture 1: Learning Systems Professor Yaser S. Abu-Mostafa California Institute of Technology, USA (LOCATION: Lance Burton Theater) 09:50 - 10:50am: Keynote Lecture 2 (from ERSA): Where Intel's Microprocessor Architecture is Going? Dr. Robert P. Colwell Independent Consultant, USA (LOCATION: Lance Burton Theater) 10:50 - 11:50am: DISCUSSION SESSIONS (general) - PDPTA'05, CDES'05 + others (Refreshments will be available) June 27 (Monday) (LOCATION: Hallways - Meeting Rooms 1-5 and 6-8) List of papers appears at the end of PDPTA'05 and CDES'05 schedules. 11:50 - 01:00pm: LUNCH (On Your Own) 01:00 - 01:15pm: ERSA OPENING REMARKS: Dr. Toomas P. Plaks (ERSA Chair), LSBU, London, UK (LOCATION: Meeting Room 1) 01:15 - 02:00pm: ERSA KEYNOTE TALK: Enabling Killer Applications of Reconfigurable Systems Donald Bouldin University of Tennessee, Knoxville, TN, USA (LOCATION: Meeting Room 1) SESSION 1-ERSA: ENERGY-EFFICIENT RECONFIGURABLE MOBILE SYSTEMS Chair: Gerard J. M. Smit, Univ. of Twente, The Netherland June 27, 2005 (Monday) (LOCATION: Meeting Room 1) 02:00 - 02:10pm: Sesion Overview, Gerard J. M. Smit 02:10 - 02:55pm: INVITED TALK: Reconfigurable Architectures for Adaptable Mobile Systems Gerard J. M. Smit University of Twente, The Netherlands (LOCATION: Meeting Room 1) 02:55 - 03:25pm: BREAK 03:25 - 4:10pm: INVITED TALK: Reconfigurable Instruction Set Computing for Embedded Processing Charle' R. Rupp Stretch, Inc., USA (LOCATION: Meeting Room 1) SESSION 1-ERSA: (cont.) ENERGY-EFFICIENT RECONFIGURABLE MOBILE SYSTEMS Chair: Gerard J. M. Smit, Univ. of Twente, The Netherland June 27, 2005 (Monday) (LOCATION: Meeting Room 1) 04:10 - 04:30pm: A SoPC Architecture of MIMO Sphere Decoder for Mobile Communications Jing Ma* and Xinming Huang University of New Orleans, New Orleans, USA 04:30 - 04:50pm: A Compact MD5 and SHA-1 Co-Implementation Utilizing Algorithm Similarities Kimmo Jarvinen*, Matti Tommiska, and Jorma Skytta Helsinki University of Technology, Finland 04:50 - 05:10pm: Rapid Arithmetic Level Simulation Based Energy Estimation for Hardware/Software Co-Design Using FPGAs Jingzhao Ou* and Viktor K. Prasanna University of Southern California, Los Angeles, CA, USA 05:10 - 05:30pm: Implementing an Adaptive Viterbi Algorithm in Coarse-Grained Reconfigurable Hardware Gerard K. Rauwerda*, Gerard J. M. Smit*, and Werner Brugger** *University of Twente, the Netherlands **Atmel Germany GmbH, Germany 06:05 - 09:30pm: Tutorial (planned) TUTORIAL 0: (June 27, Monday) Information Security Speaker: Dr. Mark Stamp (Author of Textbook, Information Security: Principles & Practice) (LOCATION: Meeting Room 6) 09:00 - 11:00pm: CONFERENCE RECEPTION DINNER - June 27 (Monday) (LOCATION: Meeting Rooms 1-5) =================================================================== June 28 June 28 June 28 June 28 June 28 June 28 June 28 June 28 =================================================================== 6:30am - 5:00pm: Registration (Second Floor, Conference Lobby: 1-5) SESSION 3-ERSA: RECONFIGURABLE SUPERCOMPUTING Chair: Maya B. Gokhale, Los Alamos National Laboratory, USA Co-Chair: Toomas P. Plaks, LSBU, UK (LOCATION: Meeting Room 1) 08:20 - 08:30am: Session Overview, Toomas P. Plaks 08:30 - 08:50am: Accelerating Exact Stochastic Simulation Using Reconfigurable Computing B. P. Thurmon*, J. M. McCollum, G. D. Peterson, C. D. Cox, N. F. Samatova, G. S. Sayler, and M. L. Simpson University of Tennessee-Knoxville, USA 08:50 - 09:10am: A 1.5-D Architecture for Back Propagation Training Sanjay Rajopadhye* and Kolin Paul** *Colorado State University, USA **Indian Institute of Technology, New Delhi, India 09:10 - 09:55am: DISTINGUISHED PAPER: Area-Efficient Evaluation of Arithmetic Expressions Using Deeply Pipelined Floating-Point Cores Ronald Scrofano*, Ling Zhuo, and Viktor K. Prasanna University of Southern California, Los Angeles, CA, USA 10:00 - 10:30am: BREAK SESSION 3-ERSA: (cont.) RECONFIGURABLE SUPERCOMPUTING Chair: Maya B. Gokhale, Los Alamos National Laboratory, USA Co-Chair: Toomas P. Plaks, LSBU, UK (LOCATION: Meeting Room 1) 10:30 - 11:15am: DISTINGUISHED PAPER: The Design And Application Of A High-End Reconfigurable Computing System Chen Chang*, John Wawrzynek, Pierre-Yves Droz, and Robert W. Brodersen University of California, Berkeley, CA, USA 11:15 - 12:00pm: DISTINGUISHED PAPER: A Library of Parameterizable Floating-Point Cores for FPGAs and Their Application to Scientific Computing Gokul Govindu*, Ronald Scrofano, and Viktor K. Prasanna University of Southern California, Los Angeles, CA, USA 12:00 - 01:00pm: LUNCH (On Your Own) 01:00 - 01:45pm: INVITED TALK: Configurable Processors and the Evolution of System-on-Chip Design Dror E. Maydan Tensilica, Inc., USA SESSION 6-ERSA: ADAPTIVE ARCHITECTURES AND APPLICATIONS Chair: Steven A. Guccione, Cmpware, Inc. USA (LOCATION: Meeting Room 1) 01:45 - 01:55pm: Session Overview, Steven A. Guccione 01:55 - 02:15pm: FPGA-Based High-Order Finite Difference Algorithm for 2D Acoustic Wave Propagation Problems Chuan He*, Wei Zhao, and Mi Lu Texas A&M university, Texas, USA 02:15 - 02:35pm: CliffoSor, an Innovative FPGA-based Architecture for Geometric Algebra A. Gentile*, S. Segreto, F. Sorbello, G. Vassallo, S. Vitabile, and V. Vullo Univ. degli studi di Palermo, Italy 02:35 - 03:05pm: INVITED TALK: Why the automotive market requires configurable computing? John Watson ElementCXI, Inc., USA 03:05 - 03:25pm: BREAK SESSION 6-ERSA: (cont.) ADAPTIVE ARCHITECTURES AND APPLICATIONS Chair: Steven A. Guccione, Cmpware, Inc. USA (LOCATION: Meeting Room 1) 03:25 - 03:45pm: Improving Security of Networked Embedded Systems Peter Athanas*, Josh Edmison*, Jonathan Graf**, Alan Jamison**, Mark Jones*, Tony Mahar*, Ben Muzal*, Cameron Patterson*, Barry Polakowski**, and Justin Stroud *Virginia Tech, Virginia, USA **Luna Innovations, Blacksburg, Virginia, USA 03:45 - 04:05pm: Cell Based Motion Estimators for Reconfigurable Platforms Wim J. C. Melis*, Kieron Turkington, Alexander Whitton, Wayne Luk, and Peter Y. K. Cheung Imperial College London, UK 04:05 - 04:25pm: Reconfigurable 1-Bit Processor Array with Reduced Wirng Area Shigeru Yamashita Nara Institute of Science and Technology, Japan 04:25 - 05:45pm: DISCUSSION SESSIONS (LOCATION: Meeting Room 1) I. SHORT PAPERS: O. A Reconfigurable Antialiasing Filter Design Using Multi-Abstraction Design Exploration Approach Otsebele Nare* and Charles Johnson-Bey Morgan State Universtiy, Baltimore, USA O. Data Partitioning for Reconfigurable Architectures with Distributed Block RAM Wenrui Gong, Yan Meng, Gang Wang, Ryan Kastner* and Timothy Sherwood University of California, Santa Barbara, CA, USA O. Instance-Specific Versus Parameter-Specific Circuit Generation Jacqueline E. Rice** and Kenneth B. Kent* *University of New Brunswick, Canada **University of Lethbridge, Canada O. Application Specific Reconfigurable Architecture Design Methodology Ali Akoglu* and Sethuraman Panchanathan Arizona State University, AZ, USA O. Architecture of Reconfigurable Algorithms Lu?s F. W. Goes*, Milene B. Carvalho, Luiz E. S. Ramos, Christiane V. Pousa, and Carlos A. P. S. Martins Pontifical Catholic Univ. of Minas Gerais, Brazil O. A Device-Controlled Dynamic Configuration Framework Supporting Heterogeneous Resource Management H. Tan* and R. F. DeMara University of Central Florida, USA O. Algorithms for Scheduling of Data Transfer Across FPGAs in a Grid Janak Porwal* and Sachin Patkar Indian Institute of Technology, Bombay, India O. A Multi-Pattern Scheduling Algorithm Yuanqing Guo*, Cornelis Hoede, and Gerard J.M. Smit University of Twente, The Netherlands II. POSTERS: O. SysteMorph: An SoC Framework for Adaptive Dynamic Optimization Systems Hamid Noori*, Kazuhito Eshima, Yousuke Fujii, Makoto Yoshida, Takeshi Soga, Norifumi Yoshimatsu, and Kazuaki Murakami Kyushu University, Japan O. A Fast Timing-Driven Router for Island-Style FPGAs Jean-Pierre Diei* and Soheil Ghiasi University of California, Davis, CA, USA O. Compiling Stream-Language Applications to a Reconfigurable Array Processor Zain-ul-Abdin* and Bertil Svensson Halmstad University, Sweden O. Design and Implementation of a Reconfigurable Computing System Environment and IP Cores for Image Processing Fang-Hsi Kuo*, Yang-Tzu Fan, Chia-Cheng Liu Jin Wen Institute of technology, Taiwan, ROC O. A Non-Linear Function Generator Using BRM Youngsoo Kim NSRI, Korea O. Application-Specific Partitioning Algorithm for Run-Time Reconfigurable Platform for Embedded Devices Krishnamoorthy Baskaran CHiPES, NTU, Singapore O. Abstract Synthesis of Turbo Decoder Elements onto Reconfigurable Circuit Caaliph Andriamisina, Catherine Dezan*, and Christophe Jego UBO, LESTER, France O. JRAS: An Efficient Compilation Tool for Reconfigurable Computing Systems Christopher C. Doss*, John Kelly, Jr.*, and Robert L. Riley, Jr.** *North Carolina A & T State University, USA **Air Force Research Laboratory, USA O. Hardware Join Java and the Formal Verification of the Compilation of Reconfigurable Computing Programs John Hopf* and David Kearney University of South Australia, Australia 06:05 - 09:30pm: Two (planned) Tutorials (concurrent sessions) - see below: TUTORIAL 1: 06:05 - 09:30pm (June 28, 2005, Tuesday) Parallel and Distributed Heterogeneous Computing Systems Speaker: Prof. H. J. Siegel, Colorado State University, USA (LOCATION: Meeting Room 1) TUTORIAL 2: 06:05 - 09:30pm (June 28, 2005, Tuesday) Grid Computing: Making the Global Cyberinfrastructure for eScience and eBusiness a Reality Speaker: Dr. Rajkumar Buyya, University of Melbourne, Australia (LOCATION: Meeting Room 2) =================================================================== June 29 June 29 June 29 June 29 June 29 June 29 June 29 June 29 =================================================================== 6:30am - 5:00pm: Registration (Second Floor, Conference Lobby: 1-5) SESSION 2-ERSA: OPERATING SYSTEM APPROACHES FOR RECONFIGURABLE HARDWARE Chair: Marco Platzner, ETH, Zurich, Switzerland Co-Chair: Christophe Bobda, Univ. of Erlangen-Nuremberg, Germany (LOCATION: Meeting Room 1) 08:20 - 08:30am: Session Overview, Marco Platzner 08:30 - 08:50am: Aspect Ratio Effects on Reconfigurable Computing Fei Wang, Jack Jean*, and Shuxia Sun Wright State University, USA 08:50 - 09:10am: Output Serialization for FPGA-Based and Coarse-Grained Processor Arrays Frank Hannig* and Juergen Teich University of Erlangen-Nuremberg, Germany 09:10 - 09:30am: Optimizing Interface Implementation Costs Using Runtime Reconfigurable Systems Stefan Ihmor* and Florian Dittmann Heinz Nixdorf Institute, University Paderborn, Germany 09:30 - 10:15am: DISTINGUISHED PAPER: Defragmenting the Module Layout of a Partially Reconfigurable Device Jan C. van der Veen*, S?ndor P. Fekete*, Mateusz Majer**, Ali Ahmadinia**, Christophe Bobda**, and J?rgen Teich** *Braunschweig University of Technology, Germany **University of Erlangen-Nuremberg, Germany 10:15 - 10:45am: BREAK SESSION 4-ERSA: RECONFIGURABLE SYSTEM-ON-CHIP AND HW/SW CODESIGN Chair: Michael J. Wirthlin, Brigham Young Univ., USA Co-Chair: Toomas P. Plaks, LSBU, London, UK (LOCATION: Meeting Room 1) 10:45 - 11:05am: Session Overview, Michael J. Wirthlin 11:05 - 11:25am: Balancing FPGA Resource Utilities Xuejun Liang*, Jeffrey S. Vetter**, Melissa C. Smith**, and Arthur S. Bland** Jackson State University, USA **Oak Ridge National Laboratory, USA 11:25 - 12:10pm: INVITED TALK: Microprocessors: The New LUT Steven A. Guccione Cmpware, Inc., USA 12:10 - 01:10pm: LUNCH (On Your Own) SESSION 4-ERSA: (cont.) RECONFIGURABLE SYSTEM-ON-CHIP AND HW/SW CODESIGN Chair: Michael J. Wirthlin, Brigham Young Univ., USA Co-Chair: Toomas P. Plaks, LSBU, London, UK (LOCATION: Meeting Room 1) 01:10 - 01:55pm: INVITED TALK: What's the Future of C-Based Programmable SoC Design? Jeff Jussel Celoxica, Inc., UK 01:55 - 02:15pm A Combined Hardware-Software Architecture for Network Flow Analysis Sherif Yusuf*, Wayne Luk*, and Geoffrey Brown** *Imperial College London, UK **Indiana University, USA 02:15 - 03:00pm: DISTINGUISHED PAPER: An Operation and Interconnection Sharing Algorithm for Partially Reconfigurable Architectures Sungjoon Jung* and Tag Gon Kim KAIST, Korea 03:00 - 03:30pm: BREAK SESSION 5-ERSA: RUNTIME RESOURCE MANAGEMENT Chair: Ronald F. DeMara, Univ. of Central Florida, USA Co-Chair: Abdel Ejnioui, Univ. of Central Florida, USA (LOCATION: Meeting Room 1) 03:30 - 03:50pm: Session Overview, Ronald F. DeMara 03:50 - 04:10pm: Performance Monitoring for Run-time Management of Reconfigurable Devices Ryan A. DeVille*, Ian Troxel, and Alan George University of Florida, USA 04:10 - 04:30pm: Improved Microarchitecture Support for Dynamic Task Scheduling on Reconfigurable Architectures Zexin Pan*, Juanjo Noguera**, and B. Earl Wells* *University of Alabama in Huntsville, USA **Hewlett-Packard Inkjet Commercial Division, Spain 04:30 - 04:50pm: Flexible Core reallocation for Virtex II Structures Yana Esteves Krasteva*, Ana Belen Jimeno, Eduardo de la Torre, and Teresa Riesgo Universidad Politecnica de Madrid, Spain 04:50 - 05:10pm: Area Reclamation Strategies and Metrics for SRAM-Based Reconfigurable Devices Abdel Ejnioui and Ronald F. DeMara* University of Central Florida, USA 05:10 - 05:30pm: FREE SLOT 05:30 - 05:45pm: ERSA CLOSING REMARKS: Toomas P. Plaks, LSBU, London, UK (LOCATION: Meeting Room 1) 06:05 - 09:30pm: Tutorial (planned) TUTORIAL 3: (June 29, 2005, Wednesday) Java Cryptography Speaker: Dr. Sub Ramakrishnan, Bowling Green State University, USA (LOCATION: Meeting Room 1) =================================================================== June 30 June 30 June 30 June 30 June 30 June 30 June 30 June 30 =================================================================== 6:30am - 5:00pm: Registration (Second Floor, Conference Lobby: 1-5) 8:20am - 6:00pm: Note: There are a number of other sessions (not listed here) that are of significant interest to ERSA conference participants (sessions belonging to other joint conferences in this event.) You are encouraged to check the schedules for other joint conferences (in particular, schedules for PDPTA'05 and CDES'05). ===================================================================