Synthesis of Reconfigurable Systems
Chairman: Martin Middendorf, Univ. of Leipzig, Germany
High-level synthesis aims to map a behavioral description of a digital system into a structural description that consists of a set of connected components called the data-path and a controller that sequences and controls the functioning of these components.
The flexibility of reconfigurable systems affects most aspects of high-level synthesis like the input description language, the internal language, or task-allocation and scheduling. Therefore new methods and systems for high-level synthesis have to be developed that can handle reconfigurabability efficiently.
focuses on the problems and challenges for the high-level synthesis of
o Cost functions for reconfigurable systems
o Optimization and design space exploration
o Partitioning and scheduling
o Resource allocation and binding
o Control synthesis
o Test, verification, and simulation approaches
o Models for reconfigurable target architectures
System Approaches for Reconfigurable Hardware
Chairman: Marco Platzner, ETH, Zurich, Switzerland
Today's reconfigurable devices offer densities of 10M gates and beyond and allow for runtime, and even partial, reconfiguration. An operating system for such a device manages the huge logic resource in a multitasking manner.
At design time, the operating system forms an additional layer in the design flow that abstracts away from hardware details and increases the level of flexibility and productivity. At runtime, the operating system constitutes online functions for task and resource management.
The purpose of this
focus session is to bring together researchers working in this rather new
field. We solicit contributions covering all issues of multitasking
reconfigurables, from theoretical aspects to prototypical implementations.
Multitasking (-threading) in reconfigurable hardware
o Modeling and specification of tasks and resources
o Offline and online task and resource management (placement, scheduling)
o Communication and interfaces
o Design tools and environments
o Case studies
Ø The JBits Experience
Chairman: Cameron Patterson, XILINX Research Labs, USA
JBits qualifies as a reconfigurable computing era, in that it enables research with mainstream FPGA architectures (such as the XC4000 and Virtex). This was in contrast to the earlier era, which focused on special architectures (such as the XC6200). Many people associate JBits only with the fundamental API to the configuration bitstream, but this is just the basic layer. Higher abstraction levels provide automatic routing, run-time parameterized cores, and many of the logic primitives available in the mainstream implementation tools. For hardware datapaths controlled by software, JBits retains most of the rapid turnaround and simplicity advantages of a pure software flow. Hardware debugging even follows the established software approaches of a core dump (BoardScope) and a hardware interpreter (DeviceSimulator).
o JBits applications
o Tools and flows using JBits
o Hardware/software co-design and co-debug
o Structural design techniques
o Hardware abstractions
Computing Architectures and Hardware
Chairman: Christian Siemers, Univ. of Applied Sciences Nordhausen, Germany
Traditionally, configurable computing was first based on PLD-, mostly FPGA-devices due to their availability. This approach is still valid with the advent of multi-million gate FPGAs due to their capacity, but constraints force now research and development to go into the direction of using architectures for configurable computing that show other features.
The purpose of this session is to understand the state of the art of alternative configurable computing architectures that support optimisation for the major constraints space, power consumption and (all kinds of) time. This specifically includes support for managing the device e.g. through operating systems, for architectures with support of distributed applications and for architectures with runtime-capable optimisations like space/time-mapping.
o Space- and/or power-efficient architectures
o Architectures for runtime-definable space/time-mapping
o Architectural support for operating system and real-time behavior
o Biology-inspired distributed architectures for configurable computing
o Architecture definition and products for general and special purpose application classes
Ø Configurable Systems-on-Chip (CSoCs)
Chairman: Jürgen Becker, Univ. of Karlsruhe, Germany
(SoC) has become reality now, driven by fast development of CMOS VLSI
technologies. Complex system integration onto one single die introduce a set of
various challenges and perspectives for industrial and academic institutions.
Important issues to be addressed here are cost-effective technologies,
efficient and application-tailored hardware/ software architectures, and
corresponding IP-based EDA methods. Recently, several CMOS designs and
implementations of complex single SoC solutions have been realized
successfully. The term SoC is still not clearly defined and used with various
interpretations in different situations. A SoC consists of two or more
microelectronic macrocomponents im-plementing complexities previously
integrated separately into different single dies. Thus, such components, also
often called IP-cores (Intellectual Property), can be distinguished by
different criteria, characterizing major aspects of SoC-level integration
- integration technology,
- signal domain, e.g. digital, analog,
- design style, e.g. full-, semi-custom, pre-diffused, pre-wired (reconfigurable) + IP-based design styles,
- computing domain, e.g. processor (time domain), dedicated ASIC-based (space domain),
(dynamically) reconfigurable (time / space domain),
- various memory-cores and technologies, and
- specification / programming method, e.g. high-level language HLL, Assembler, hardware languages HDL
Today´s microelectronic system designers prefer currently ASIC-based SoCs, consisting mainly of processor-, memory-, and dedicated ASIC-cores. Recently, in addition to ASIC-based, one new promising type of SoC architecture template is recognized by several academic and first commercial versions: Configurable SoCs (CSoCs), consisting of processor-, memory-, probably ASIC-cores, and on-chip reconfigurable hardware parts for customization to a particular application. CSoCs combine the advantages of both: ASIC-based SoCs and multichip-board development using standard components, e.g. they require only minimal NRE costs, because they don´t need expensice ASIC-tools for developing always different and in the future very expensive mask sets, everytime the functionality or standards are changing. Thus, besides other advantages, an enormous cost and risk minimization perspective is obvious for industrial CSoCs. Moreover, some changes for traditional chip design flows are influencing today’s egineering education. Multidisciplinary system thinking is required for future designs, e.g. such system architects should be able to operate efficiently in interdisciplinary teams with highly soft-skilled members, required more and more by today´s embedded systems divisions. This focus session is looking for contributions on recent academic and commercial developments in CSoC architectures, technologies, education schemes, and application perspectives in various areas.
o Application-tailored Configurable Datapath
and Circuit Structures
o Communication Interface Synthesis and SoC Integration
o IP-based Hardware/Software Co-Engineering and SoC Integration Trade-offs
o Reconfigurable Instruction Set Integration for Processor-Cores
o Adaptivity, Self-Repairing and Testing Concepts for CSoCs
o CSoC Applications, Prototyping and Industrial Aspects
Reconfigurable Systems to Adaptive Systems
Chairman: Steven Guccione, QuickSilver Tech., Inc., USA
Email: Steven Guccione@nospam.qstech.com
From its research beginnings nearly two decades ago, the area of Reconfigurable Computing has been closely tied to Field Programmable Gate Array (FPGA) hardware. This device, available in a variety of forms from a variety of vendors, has been the workhorse of researchers and early adopters of this technology. As reconfigurable systems have matured, a trend away from the highly programmable Look-Up Table (LUT) based arrays and toward more computation-oriented devices can be observed. These new ACM devices seek to address limitations in size, power and performance of existing FPGA devices by taking approaches as varied as configurable data paths to homogeneous and heterogeneous arrays. This larger-grained approach also shifts the emphasis in design tools away from traditional place and route circuit design tools and towards a more software-like programming model.
o Fine-grain and
o System on Chip archit ectures
o Hybrid architectures
o Novel applications
Power Systems Using FPGAs
Chairman: Ju-wook Jang, Sogang University, Korea
increase in available processing power, FPGAs become an attractive fabric for implementing
complex and compute intensive applications such as signal processing kernels
for mobile devices. Therefore, in addition to time performance, power
performance is a key performance metric. However, unlike the field of low power
system design for ASIC, a lot of work is yet to done in the field of lower
power system design in FPGA. These include modeling of power consumption,
design methodology, optimization techniques, applications and new here the
future research effort should be directed in the field of lower power systems
o Power/energy consumption
modeling for FPGA devices
o Optimization techniques for Power/energy dissipation on FPGA
o Estimation of power consumption for designs on FPGA devices
o Low power/energy applications on FPGA
o Design methodology for low power/energy consumption for FPGA
o Low power implementation of network protocols using FPGA
o Low power implementation of multimedia processing using FPGA
o Other related issues
Reconfigurable Floating Point Processing
Chairman: Maya Gokhale, Los Alamos National Laboratory, USA
Traditionally, reconfigurable computing engines have excelled at data intensive fixed point and bit-oriented computation. A necessary step to port a signal or image processing application to a reconfigurable platform has been dynamic range analysis of a floating point application to determine suitable fixed point data formats.
With the advent of multi-million gate FPGAs and PLD's, it has become feasible to perform floating point operations directly on reconfigurable devices. Leading FPGA and reconfigurable computer vendors offer floating point libraries for their products.
The purpose of this session is to understand the state of the art for reconfigurable floating point processing. We solicit papers that evaluate the benefits and drawbacks of using floating point data types in reconfigurable computing applications.
Topics (but are not limited to)
o Customizable floating point libraries
o Fixed point/floating point tradeoffs in area, clock frequency, power
o Experience with use of floating point on reconfigurable devices for DSP, supercomputing or other applications
o Experience with mixed mode fixed/floating point applications
o Tools to infer optimal application-specific floating point sizes for mantissa and exponent
o Customized error handling in floating point arithmetic
o Reconfigurable cell architectures optimized for floating point
o Other floating point related topics : architectures, tools, applications
Ø Software Defined Radio
Chairman: Jeffrey Reed, Virginia Tech., USA
Software defined radio (SDR) has evolved as multimode, software programmable radios allowing global roaming and as a platform for the rapid introduction of new services into existing wireless communication networks. SDR therefore promises mobile communication networks a major increase in flexibility and capability.
Conventional software radios achieve flexibility through the use of software on static hardware. Recent advances in reconfigurable hardware have shown possibilities of increasing the flexibility of software radio functionalities in terms of reconfigurable radio architecture, run time configuration and over the air download features.
This session is intended to understand the applications of the state of the art in reconfigurable systems to software radio design.
o Design methodologies for reconfigurable
o Custom Computing Machines (CCM) for Software Radios
o Flexible interconnects for high bandwidth I/O
o VLSI architectures for numerical communication algorithms in Software radios eg: SVD, CORDIC
o Software communication architecture (SCA) implementation on CCMs
o Performance evaluation of radio architectures using DSPs FPGAs and CCMs
o Issues with downloadable run time configuration
o Software/Hardware Verification
Ø Custom Computing Machines for Image
Chairman: Marek Gorgon, AGH University of Technology, Krakow, Poland
The continuous increase of expectations regarding Image Processing, Image Compression and 2D -Display Systems in particular combination of requirements such as parallelizm, flexibility, reconfigurability makes high capacity FPGA devices more and more attractive alternative rather than other hardware and especially software based solutions.
Simultaneously, software tools for efficient design of FPGA-based imaging systems are being carefully examined. Special attention is paid to approaches such as IP Cores, Software-hardware libraries, dedicated software extensions.
The purpose of this
session is to revise and summarize the state of the art of and Image Processing
Systems based on the new generation FPGA devices.
o Reconfigurable Architectures
for Image Processing
o Complex Image Processing Algorithms for CCM
o Real-time Imaging: Run Time Reconfiguration and Software/Hardware Systems
o FPGA-based modules, libraries and IP Cores for Image Processing
o FPGA-based Image Compression
o Image co-processors and display accelerators