Contents
Ø
Collaborative and Reconfigurable Object Tracking
Prof. Majid Sarrafzadeh, UCLA, USA
Ø
PACT XPP
Architecture in Adaptive System-on-Chip Integration
Prof. Jürgen Becker, Univ. of Karlsruhe,
Germany
Ø Latest Developments at
QuickSilver Tech.
Dr. Steven A. Guccione, QuickSilver Tech.,
Inc., USA
Ø Altera FPGA Technology Provides Innovative Solution for
Evolving Market Needs
Razak
Mohammedali, Altera Corporation, San Jose,
USA
Ø
Servers for
Embedded Platform FPGAs
Dr. Cameron Patterson, XILINX Research Labs,
USA
Ø Collaborative
and Reconfigurable Object Tracking
Prof. Majid Sarrafzadeh, UCLA, USA
Abstract
Today's
embedded systems contain various combinations of different sub-systems, such as
ASICs, microprocessors, DSPs, and reconfigurable cores. New embedded systems
require a larger amount of flexibility as compared to their predecessors.
Markets change very rapidly demanding embedded system solutions that are easily
alterable. Such solutions are expected to support a variety of applications,
changing system requirements and standards as well as altering operating
conditions.
In
this talk we study various trade offs existing in embedded/reconfigurable vs.
traditional processor-based computing schemes in a collaborative signal
processing system. We will discuss a system that has been developed using a
network of cameras with embedded processors. The required image processing
algorithms have been adapted to the constrained embedded processors.
Bio
Majid Sarrafzadeh (M'87, SM'92, F'96) received his B.S., M.S.
and Ph.D. in 1982, 1984, and 1987 respectively from the University of Illinois
at Urbana-Champaign in Electrical and Computer Engineering. He joined Northwestern University as an
Assistant Professor in 1987. In 2000,
he joined the Computer Science Department at University of California at Los
Angeles (UCLA). His recent research
interests lie in the area of Embedded and Reconfigurable Computing, VLSI CAD,
and design and analysis of algorithms. Dr. Sarrafzadeh is a Fellow of IEEE for
his contribution to "Theory and Practice of VLSI Design". He received an NSF Engineering Initiation
award, two distinguished paper awards in ICCAD, and the best paper award in
DAC. He has served on the technical program committee of numerous conferences
in the area of VLSI Design and CAD, including ICCAD, DAC, EDAC, ISPD, FPGA, and
DesignCon. He has served as committee
chairs of a number of these conferences. He is on the executive
committee/steering committee of several conferences such as ICCAD, ISPD, and
ISQED.
Professor
Sarrafzadeh has published approximately 250 papers, is a co-editor of the book
"Algorithmic Aspects of VLSI Layout" (1994 by World Scientific), and
co-author of the book "An Introduction to VLSI Physical Design" (1996
by McGraw Hill). Dr. Sarrafzadeh is on the editorial board of the VLSI Design
Journal, an Associate Editor of ACM Transaction on Design Automation (TODAES)
and an Associate Editor of IEEE Transactions on Computer-Aided Design (TCAD).
Dr.
Sarrafzadeh has collaborated with many industries in the past fifteen years including
IBM and Motorola and many CAD industries and was the architect of the physical
design subsystem of Monterey Design Systems' main product.
Ø PACT XPP
Architecture in Adaptive System-on-Chip Integration
Prof. Jürgen Becker, Univ. of Karlsruhe, Germany
This talk gives the actual status and results of a
dynamically Configurable System-on-Chip (CSoC) integration, consisting of a
SPARC-compatible LEON processor-core, a commercial coarse-grain XPP-array of
suitable size from PACT XPP Technologies AG (Muenchen, Germany), and
application-tailored global/local memory topology with efficient multi-layer
Amba-based communication interfaces. The talk will also focus on PACT´s
XPP architecture realizing a new runtime reconfigurable data processing
technology that replaces the concept of instruction sequencing by configuration
sequencing with high performance application areas envisioned from embedded
signal processing to co-processing in different DSP-like and mobile
application environments. The underlying programming model is motivated by the
fact, that future oriented applications need to process streams of data
decomposed into smaller sequences which are processed in parallel. The XPP
architecture is regular structured for arbitrarily sized implementations,
including regularity in combination with locality of data processing,
e.g. for reducing power consumption. The complte adaptive SoC
architecture is synthesized within an industrial/academic project onto 0.18 and
0.13 mm UMC CMOS technologies at Universitaet Karlsruhe (TH). Due to
exponential increasing CMOS mask costs, essential aspects for the industry are
now adaptivity and cost-efficiency of SoCs, which can be realized by
integrating reconfigurable re-usable hardware parts on different granularities
into Configurable Systems-on-Chip (CSoCs).
Bio
Juergen Becker received the Diploma degree in 1992, and his
Ph.D. (Dr.-Ing.) degree in 1997, both at Kaiserslautern University, Germany.
His research work focused on application development environments for
reconfigurable accelerators and included hardware/software codesign,
parallelizing compilers, customized computing, and high-level synthesis. He has
been local administrator for the European Design Project EUROCHIP in 1993/95.
In 1997 Dr. Becker joined the Institute of Microelectronic Systems at Darmstadt
University of Technology, Germany, as assistant professor, where he taught CAD
algorithms for VLSI design. He did research in Systems-on-Chip (SoC) architectures
and tools focused on dynamical reconfigurable technologies for mobile
communication systems. Since 2001 Juergen Becker is professor for embedded
electronic systems at the Institut fuer Technik der Informationsverarbeitung
(ITIV) at Universitaet Karlsruhe (TH). He gives lectures in digital design
(undergraduate level), in CAD algorithms for high-level synthesis and VLSI
design, hardware/software codesign, as well as in bus interfaces and protocols
(graduate level). His actual research is focused on industrial-driven SoC
integration with emphasis on new dynamical reconfigurable hardware
architectures, incl. corresponding hardware/software co-design and co-synthesis
techniques from high-level specifications, as well as low power SoC
optimization. Prof. Becker is author and co-author of
more than 100 scientific papers, published in peer-reviewed international
journals and conferences. He is active in several technical program and
steering committees of international conferences and workshops. He is a Member
of the german GI and Senior Member of the IEEE. Prof. Becker is chair of the
GI/ITG Technical Committee of “Architekturen fuer hochintegrierte Schaltungen”
and managing co-director of the “International Departmemt” at Universitaet
Karlsruhe, Germany.
Ø Latest
Developments at QuickSilver Tech.
Dr. Steven A. Guccione, QuickSilver Tech., Inc., USA
Abstract
Reconfigurable systems are currently undergoing an
evolution. Architectures are moving
away from Look-Up Table (LUT) based hardware to larger grained approaches. This shift not only makes faster, more
energy efficient designs possible, but potentially shifts the tools approach
away from a hardware-based circuit-design model towards a software
program-design one. QuickSilver
Technology is currently at the forefront of this trend with its Adaptive
Computing Machine (ACM) architecture.
The ACM is designed to provide a high-performance, fully-programmable,
low-power solution surpassing traditional Digital Signal Processors (DSP) and
approaching, and sometimes even surpassing, Application Specific Integrated
Circuits (ASICs) in both performance and energy efficiency. The ACM architecture is based on a
hetereogeneous processor array communicating across an on-chip network. In order to fully take advantage of the
capabilities of this device, a tool suite combining traditional elements such
as simulators, emulators, compilers, assemblers and debuggers as well as more
sophisticated analysis and resource management support is provided. In real-world applications, this system has
demonstrated a price / power / performance ratio currently unattainable in
other systems.
Bio
Dr. Steven A. Guccione is a Senior Staff Engineer at
QuickSilver Technology, Inc. His interests are in high performance computing,
in particular software tools for reconfigurable computing. Dr. Guccione
received his Bachelor of Science degree in Electrical and Computer Engineering
from Boston University, his Master of Science degree in Electrical Engineering
from the University of Minnesota and his Ph.D. degree in Electrical Engineering
from the University of Texas at Austin.
His Ph.D. dissertation, Programming Fine-Grained Reconfigurable
Architectures was an early contribution in the field of reconfigurable
computing, and one of the first to address software and system issues. Dr. Guccione has approximately 30 published
papers in this field as well as approximately a dozen issued patents. He has previously held engineering positions
Xilinx, where he worked on the XC6200 and was the engineering lead on their JBits
project. Dr. Guccione has also held
engineering positions at Texas Instruments, Honeywell, Advanced Micro Devices,
IBM, MCC/Motorola and has consulted for several smaller companies.
Ø
Altera FPGA Technology Provides Innovative Solution for Evolving Market
Needs
Razak Mohammedali, Altera
Corporation, San Jose, USA
Ø Servers for Embedded
Platform FPGAs
Dr. Cameron Patterson, XILINX Research Labs, USA
Most
reconfigurable computing applications require substantial host computer
resources. Although a PC or workstation host suits development, it can be
difficult to port the application to an embedded environment. The
transition is easier if a client/server model is used for both development and
deployment of reconfigurable systems. Network infrastructure often
already exists when current platform FPGAs are used in embedded
environments. A prototype system has been developed where the server
accesses the M5.1i physical design database. Clients request database
updates using logic, net and module abstractions. The corresponding
partial bitstreams are quickly generated, since the overheads of loading
databases and processing the entire design are avoided.
Bio
Cameron Patterson received the B.Sc. (Honours) and M.Sc.
degrees in Computer Science from the University of Manitoba, Canada, in 1980
and 1983 respectively, and the Ph.D. degree in Computer Science from the
University of Calgary, Canada, in 1992.
From 1992 to 1994, he held an NSERC Industrial Research
Fellowship at the Alberta Microelectronic Centre in Canada. During this time
he developed software to partition circuits over multiple FPGAs, lectured on
VLSI design at the University of Calgary, and was on the technical program
committee for the 1993 Canadian Conference on VLSI. He joined Xilinx in
1994, and has worked on both the XC6200 and JBits reconfigurable computing
projects. Currently, he is exploring run-time improvements to the
mainstream Xilinx implementation tools.