Introduction

The recent  years have  shown a growing interest in using reconfigurable computing platform (FPGAs) for the design of application-specific computer systems. The  custom computing systems on the reconfigurable platform has often achieved the performance several orders of magnitude higher than the traditional processor based solutions. Now the time arises for the breakthrough of reconfigurable computing into mass markets of application-specific systems and information appliances, which include emerging areas like mobile communication, multimedia-based networks, encryption,image processing etc.

The significant advantage of reconfigurable computing has been achieved mainly because of  three reasons.

1. Implementing of algorithms directly in hardware, on the level of circuits, thus,  without control overhead. As a result, the computational density is an order of magnitude higher than in conventional processors.

2. Parallelism is the nature of hardware. Implementing algorithms in hardware  means the massive use of parallelism. As the computing space is large and reconfigurable, the high degree of parallelism and efficient implementation are easily achievable.

3. The flexible, fast and risk-minimized way to synthesize application-specific multi-purpose hardware (``time-to-market").

The advances in reconfigurable computing architecture, in algorithm implementation methods, and in automatic mapping methods of algorithms into   hardware and processor spaces form together a new paradigm of computing and programming   that has often been called  `Computing in Space and Time' or `Computing without Computer'.
 

Scope

This conference focuses on the different approaches in engineering of reconfigurable systems and implementing of algorithms, i.e. on this new paradigm of computing, including theory,
architecture, algorithms, design systems and applications that demonstrate the benefits of reconfigurable computing.
 

Topics

The topics of interest include, but are not limited to:
 

1. Theory, Mapping and Parallelization. Mapping algorithms into hardware, space-time mapping and synthesis of regular arrays, IP based methods, dataflow and functional programming approaches, logical specification and verification, developing correct circuits, the impact of reconfigurable hardware architectures onto algorithm parallelization, biologically inspired methods etc.
2. System Architectures, Aspects and Evaluation. Complex systems  using reconfigurable processors, application-tailored reconfigurable Systems-on-Chip (SoC),  architectures of SoCs, adaptive and evolvable systems, rapid  system prototyping etc.
3. CAD: Specification, Partitioning and Synthesis. Hardware compilation, hardware/software codesign, IP-based  specification and mapping methods for reconfigurable systems, object oriented  models and mapping methods, hardware description languages, design environments and interfaces etc.
4. Reconfigurable Hardware Architectures.  Dynamically  reconfigurable hardware architectures, reconfigurable processor architectures,   compiled accelerators, performance evaluation  of reconfigurable SoCs,  application-specific communication interfaces of reconfigurable SoCs, low power evaluation and optimization of reconfigurable systems, fault-tolerance  using reconfigurable hardware,  trade-offs measurements etc.
5. Algorithms and Optimization. Newly developed algorithms for efficient implementation on reconfigurable systems, in hardware, in space and time, algorithms for design optimization etc.
6. Applications. Possible applications areas of interest include, but are not limited to:  Classical image and signal processing ---digital filters, edge and line detection, morphological operators, motion and stereo estimation, discrete transformations,linear algebra, radar systems, object recognition etc. Multimedia and virtual reality --- telecommunication, data compression, video imaging,  image databases, computational geometry and  computer graphics, software radio, digital libraries, genetic databases etc.  Automotive industry --- lane detection and obstacle detection, vehicle guidance, traffic systems, object recognition, navigation of robots etc.  Security systems --- object recognition and tracking, cryptology, Internet and security etc.

Exhibition

An exhibition is planned for the duration of the MultiConferences. Interested parties should contact ERSA Co-Chair T. Plaks or the MultiConferences General Chair H. R. Arabnia (hra@cs.uga.edu). All exhibitors will be considered to be the co-sponsors of the conferences.
 
 

Important Dates

• Draft papers:(about 4-5 pages):      February 25, 2001
• Notification of acceptance:             April 2, 2001
• Camera-ready papers (7 pages):    May 1, 2001
• Conference:                                   June 25-28, 2001

 

Submission

Prospective authors are invited to submit an electronic copy of  original, unpublished work in Postscript or in pdf format. Each paper must indicate the number and name of the topic area to which it should belong. Each submission must include a cover letter containing  the title of paper, authors with their affiliations and the topic area. Also, please indicate  the contacting author's name, full postal address and email address.
There are two ways for submission:

• Anonymous ftp: ersa.sbu.ac.uk
• Email: ersa@sbu.ac.uk

If you have any questions or problems about these instructions, please do not hesitate to email: ersa@sbu.ac.uk or directly to conference chair Toomas Plaks: plakst@sbu.ac.uk.

All accepted papers will be published in the proceedings of conference. After the conference, authors of best papers will be invited to submit an extended version for publication in an International Journal (last year was The Journal of Supercomputing).
 

Conference Chairs

Dr. Toomas P. Plaks                  Prof. Peter M. Athanas
South Bank Univ.                       Virginia Tech.
London                                      USA

email: plakst@sbu.ac.uk             email: athanas@vt.edu
 

Steering Committee

Jürgen Becker Gordon Brebner  Apostolos Dollas Hossam ElGindy Dominique Lavenier Wayne Luk  Martin Middendorf	Darmstadt Univ. of Technology, Germany Univ. of Edinburgh, Scotland Technical Univ. of Crete, Greece Univ. of New South Wales, Australia IRISA, France Imperial College, UK Univ. of Karlsruhe, Germany

Programme Committee

Peter Athanas Christophe Beaumont Jürgen Becker Gordon Brebner  Oliver Diessel Hossam ElGindy Jifeng He Jack Jean Richard Katz Rainer Kress Dominique Lavenier Miriam Leeser  Björn Lisper Wayne Luk  Graham  Megson Martin Middendorf  Toomas Plaks Marco Platzner Bernard Pottier Jürgen  Teich Lothar Thiele Serge Vernalde Markus Weinhardt Michael Wirthlin	Virginia Tech., USA  Virtual Computer Corporation, USA Darmstadt Univ. of Technology, Germany Univ. of Edinburgh, Scotland  Univ. of New South Wales, Australia Univ. of New South Wales, Australia United Nations Univ., Macau Wright State Univ., USA NASA Goddard Space Flight Center, USA Infineon technologies, Germany IRISA, France Northeastern Univ., USA  Univ. of Mälardalen, Sweden Imperial College, UK The Univ. of Reading, UK Univ. of Karlsruhe, Germany South Bank Univ., UK ETH, Zurich, Switzerland  Univ. of Bretagne Occidentale, France Univ. of Paderborn, Germany ETH, Zurich, Switzerland IMEC, Leuven, Belgium  PACT Informationstechologie GmbH, Germany Brigham Young Univ., USA

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