Senior Lecturer Department of Software Development and Computer Networking  South Bank University, London 103 Borough Road, London SE1 0AA, UK plakst@lsbu.ac.uk Tel: +44 (0) 20-7815 7495 Fax: +44 (0) 20-7815 7495

• IR7, Int. Registered Techn. Specialist in Computer Science,  Int. Techn. Inst., San Diego, USA
• Ph.D., Computer Engineering, Chalmers Univ. of Techn., Gothenburg, Sweden
• M.Eng, Computer Engineering (Cum Laude), Tallinn Techn. Univ., Tallinn, Estonia
• Member of the New York Academy of Science
• Member of the IEEE and the IEEE Computer Society
• Member of the  ACM SIGDA  U.K. chapter

  Honors and Awards 

• Dr. Plaks biography is published in the
• 8th Edition of Marquis "Who's Who in Science and Engineering", USA, 2005-2006;
• 20th Edition of Marquis "Who's Who in the World", USA, 2005, 2003;
• 31st Edition of the "Dictionary of International Biography", 2004, IBC, England.

• Achievement Award. The World Academy of Sciences,  USA, 2004, 2003

• Operating Systems
• Computer Networks
• Computer Architecture
  

• EE -- ERSA ENTERPRISE -- Engineering of Reconfigurable Systems and Algorithms


We are  soliciting people willing to review papers for conferences and for other similar events. If you would like to be a reviewer, please e-mail to  Toomas Plaks (plakst@sbu.ac.uk) a list of your research areas and a short CV.
 

Founder and Guest Editor of a Series of Special Issues

• Guest Editor, Special Issue on  Engineering of Configurable Systems IV. The Journal of Supercomputing. Vol. 32, No. 2, pp. 103-184, May 2005.
• Guest Editor, Special Issue on  Engineering of Configurable Systems III. The Journal of Supercomputing. Vol. 30, No. 3, pp.  211-305, Dec. 2004.
• Guest Editor, Special Issue on  Engineering of Configurable Systems II. The Journal of Supercomputing. Vol. 26, No. 3, pp. 219-332, Nov. 2003.
• Guest Editor, Special Issue on  Engineering of Configurable Systems I. The Journal of Supercomputing. Vol 26, No. 2, pp. 107-203, Sept. 2003.
• Guest Editor, Special Issue on  Engineering of Reconfigurable Systems. The Journal of Supercomputing. Vol. 21, No. 2, pp. 113-190,  Feb. 2002.
• Guest Editor, Special Issue on  Engineering of Reconfigurable Hardware/Software Objects.The Journal of Supercomputing. Vol. 19, No. 1, pp. 1-140, May 2001.
• Guest Editor, Special Issue on Advanced Regular Array Design, Journal of Parallel Algorithms and Applications. Vol. 15, No. 3-4, pp. 131-300, 2000.

Current Professional Services

• Guest Editor. Configurable Computing Design. Special Section on IEEE Transaction on VLSI Systems. Submission deadline: May 1, 2006.
  Possible publication date: Nov. 2006.
  
• Founder and Chairman. The International Conference on Engineering of Reconfigurable Systems and Algorithms, ERSA. Las Vegas, USA, Since 1999.
• Chairman and Initiator. Mobile Computing Hardware Architectures, Design and Implementation, MOCHA Design, IEEE HICSS, Hawaii, 2005, 2006, 2007.
• Vice Chair. Embedded Parallel Systems, Euro-Par 2006, Dresden, Germany. 29th Aug. - 1st Sept. 2006.
  
• Member of Editorial Board. International Journal of Parallel, Emergent and Distributed Systems (IJPEDS). Taylor & Francis Group plc, UK.
• Member of Technical Committee. IASTED  Technical Committee on Parallel and Distributed Computing Systems,  2003-2006.
• Member of Technical Committee. The annual Military and Aerospace Programmable Logic Devices (MAPLD) International Conference, Ronald Reagan Building and International Trade Center, Washington, D.C., USA, Since 2001.

Areas of Interest

• Massively Parallel Computer Systems - Regular Algorithms and Architectures
  Theory and Design of  Regular/Systolic Processor Array
  
• Algorithm Engineering - Implementing Algorithms on VLSI, FPGAs, Multi-core Processors
  
CAD Systems, Hardware/Software Co-Design
• Reconfigurable Architectures; Custom Computing Machines; Cellular Spaces
Computing in Space and Time
• High-Performance Application-Specific Systems: Multimedia, Signal, Image andVideo Processing,
Computer Graphics; Computational Geometry

Publications

An author or co-author of more than 80 scientific papers.

Academic  Monographs:

1. Toomas P. Plaks. Piecewise Regular Arrays. Application-Specific Computations. Parallel Processing Series, Volume 1. Gordon and Breach Science Publishers. 266 pages, 1999.
   

1. Engineering of Reconfigurable Systems and Algorithms. Proc. of the International Conference.  Toomas P. Plaks, Editor, CSREA Press, 2005, 280 pages.
2. Engineering of Reconfigurable Systems and Algorithms. Proc. of the International Conference.  Toomas P. Plaks, Editor, CSREA Press, 2004, 334 pages.
3. Engineering of Reconfigurable Systems and Algorithms. Proc. of the International Conference.  Toomas P. Plaks, Editor, CSREA Press, 2003, 340 pages.
4. Engineering of Reconfigurable Systems and Algorithms. Proc. of the International Conference.  Toomas P. Plaks and Peter M. Athanas, Editors, CSREA Press, 2002, 220 pages.
5. Engineering of Reconfigurable Systems and Algorithms. Proc. of the International Conference.  Toomas P. Plaks and Peter M. Athanas, Editors, CSREA Press, 2001, 130 pages.

1. Toomas P. Plaks. Configuring of Algorithms in Mapping into Hardware. Journal of Supercomputing, 21(2), pp. 161-177,  Feb. 2002.
2. Toomas P. Plaks. Efficient Mapping Reductions Using Iso-Planes on the Polytope Model. Journal of Parallel Algorithms and Applications, 13(4): 321-343, 1999.
3. Toomas P. Plaks. Mesh of linear arrays for template matching. Real-Time Imaging Journal, 6(2): 373-382, Academic Press, December 1996.

1. Toomas P. Plaks. Configuring of Algorithms in Space and Time. In  Proc. of The Fourth International Workshop on Advanced Parallel Processing Technologies, September 17 - 19, 2001, Ilmenau, Germany.
2. Toomas P. Plaks. Spatially Reconfigurable Module for FIR Filters. In  SPIE ITCom 2001, Reconfigurable Technology: FPGAs and Reconfigurable Processors for Computing and Communication III, Aug. 19-24, 2001, Denver, CO, USA, John Schewel, Peter M. Athanas, Philip B. James-Roxby, John T. McHenry, Editors, Proc. SPIE Vol. 4525, 2001.
3. Toomas P. Plaks. Algebraic Transformations in Regular Array Design. In COMPSAC’2001. Proc. of The Annual International Computer Software and Applications Conference, Oct. 8-12, 2001, Chicago, USA. IEEE Computer Society Press, 2001.
4. Toomas P. Plaks. Configurable Hardware Modules. In ERSA'01. The  International Conference on Engineering of Reconfigurable Systems and Algorithms, June 25-28, 2001, Las Vegas, USA, pages 99-102. CSREA Press, 2001.
5. Toomas P. Plaks. Implementing Algorithms on Multilayered Reconfigurable Arrays. In  MAPLD 2000. Proc. of The 3rd Annual Military and Aerospace Applications of Programmable Devices and Technologies International Conference, September 26-28, 2000, Laurel, Maryland, USA.(CD-ROM)
6. Toomas P. Plaks. Parallel k-Mismatching of Strings Using Daughter-board Structure. In  Reconfigurable Technology: FPGAs for Computing and Applications II, 5-8 November 2000, Boston,  Massachusetts, USA, J. Schewel, P. Athanas, Ch. Dick, J. McHenry, Editors, Proc. SPIE Vol. 4212, pages 104-115, 2000.
7. Toomas P. Plaks. Formal Derivation of Multilayered Hardware/Software Structures. In IEEE ICFEM 2000. Proc. of Third IEEE International Conference on Formal Engineering Methods, 4--7 Sept. 2000, York, UK. Pages 5-13. IEEE Computer Society Press, 2000.
8. Toomas P. Plaks. Designing High-Performance Application-Specific Processors.  In  SSGRR-2000. Proc. of the International Conference on Advances in Infrastructure for Electronic Business, Science, and Education on the Internet, July 31 -- Aug. 6, 2000, l'Aquila, Italy. (CD-ROM)
9. J.O. Cadenas, G.M. Megson and T.P. Plaks. Accelerating JPEG Compression with a Dynamically Reconfigurable Systolic Array.In PDPTA'2000. Proc. of the Int. Conf. on Parallel and Distributed Processing Techniques and Applications, June 26--June 29, 2000, Las Vegas, USA. CSREA Press, 2000.
10. Toomas P. Plaks, Graham M. Megson, Vassil N. Alexandrov.  A family of efficient regular arrays for band and sparse matrix inversion using Monte Carlo methods.  In 16th  IMACS World Congress  2000 on Scientific Computation, Applied Mathematics and Simulation, Lausanne, Switzerland, August 21-25, 2000. (CD-ROM), 6 pages, IMACS, EPFL, 2000.
11. Jose O. Cadenas, Graham M. Megson and Toomas P. Plaks.  Quantitative evaluation of three reconfiguration strategies on FPGAs: A case study. In  HPC-Asia 2000. Proc. of the Fourth Int. Conf. on High-Performance Computing in the Asia-Pacific Region, 14--17 May, 2000, Beijing, China. Vol. I, pages 337--342. IEEE Computer Society Press, 2000.
12. Toomas P. Plaks, Oswaldo Cadenas and Graham M. Megson. Experiences Using Reconfigurable FPGAs in Implementing Monte-Carlo Methods. In PDPTA'99. Proc. of the Int. Conf. on Parallel and Distributed Processing Techniques and Applications, June 28-July 1, 1999, Las Vegas, USA, CSREA Press, 1999.
13. Toomas P. Plaks. Mapping Regular Algorithms onto Multilayered 3-D Reconfigurable Processor Array. In HICSS'99. Proc. of the 32nd Hawai'i Int. Conf. on System Sciences, Jan. 5-8, 1999, Maui, Hawaii, IEEE Computer Society Press, 1999.