NB!  CONFERENCE ROOM LOCATION WILL BE CHANGED!
 
 

JUNE 23, 2002 (SUNDAY)
 

06:00 - 09:00pm:  REGISTRATION(Second Floor, Conference Section)

JUNE 24, 2002 (MONDAY)
 

06:30am - 6:00pm:  REGISTRATION(Second Floor, Conference Section)

08:25 - 08:40am:   MultiConference Opening Remarks
                Hamid R. Arabnia (Chair, 2002 Int'l MultiConference),
                 University of Georgia, Athens, Georgia, USA
                (Location: Meeting Rooms: 1 - 5)

08:40 - 09:40am:   MultiConference Keynote Lecture 1:
                A Grand Challenge and Grand Opportunity
                Professor Ryszard S. Michalski, George Mason University, USA
                (Location: Lance Burton Theatre )

09:45 - 10:45am:  MultiConference Keynote Lecture 2:
                The Next Big Leap in Reconfigurable Systems
                Paul Master, CTO, QuickSilver Technology, USA
                (Location: Lance Burton Theatre )
 

SESSIONS
 

10:45 - 11:45am:  A-ERSA: DISCUSSION SESSION + REFRESHMENTS
                 RRR + SRP + Posters  (List of papers appears at the end of conference program.)
                 (Location: Meeting Rooms: 1 - 5)
 
 

11:45 - 12:40pm: LUNCH (On Your Own)
 
 

9:00 - 11:00:  CONFERENCE RECEPTION DINNER
                 (Location: Meeting Rooms: 1 - 5)
 

JUNE 25, 2002 (TUESDAY)
 
 

01:40 - 02:00pm:  ERSA Opening Remarks
             Conference Chairs: Toomas P Plaks and Peter M. Athanas
 

02:00 - 04:00pm

SESSION 1-ERSA:   Space-Based Reconfigurable Computing  (Space)
                         Chairman: Maya Gokhale, Los Alamos National Laboratory, USA
                         (Location: Conference Room F)

02:00 - 02:20pm:  A Space Based Reconfigurable Radio
                 Michael Caffrey;
                 Los Alamos National Laboratory, USA

02:20 - 02:40pm:  A Reconfigurable Computing Fabric
                 Christophe Wolinski, Maya Gokhale and Kevin McCabe;
                 Los Alamos National Laboratory, USA

02:40 - 03:00pm:  MATLAB-Based VHDL Development Environment
                 Kim Katko and Scott H. Robinson;
                 Los Alamos National Laboratory, USA

03:00 - 03:20pm:  Single-Event Upset Simulation on an FPGA
                 Eric Johnson*, Michael J. Wirthlin* and Michael Caffrey**;
                 *Brigham Young Univ., USA;
                 **Los Alamos National Laboratory, USA

03:20 - 03:40pm:  BREAK

03:40 - 04:00pm:   Implementing High Speed Matrix Processing on a Reconfigurable Parallel Dataflow Processor
                 Fredrik Gunnarsson, Christian Hansson, Dennis Johnsson and Bertil Svensson;
                 Halmstad Univ., Sweden
 
 

04:00 - 06:00pm

SESSION 2-ERSA:   Configurable Systems-on-Chip (CSoCs)
                         Chairman: Jürgen Becker, Univ. of Karlsruhe, Germany
                         (Location: Conference Room F)

04:00 - 04:20pm:  The Universal Configurable Block/Machine - An Approach for a Configurable SoC--Architecture
                 Christian Siemers;
                 Univ. of Applied Sciences Nordhausen, Germany

04:20 - 04:40pm:  Max-log-MAP Mapping on an FPFA
                 Paul M. Heysters, Lodewijk T. Smit, Gerard J.M. Smit and Paul J.M. Havinga;
                 Univ. of Twente, The Netherlands

04:40 - 05:00pm:  Designing and Mapping of a Turbo Decoder for 3G Mobile Systems Using Dynamically Reconfigurable      Architecture
                 Mingwei Ding, Ahmad Alsolaim and Janusz Starzyk;
                 Ohio Univ., USA

05:00 - 05:20pm:  Hardware Design - On the Way to Mobile 'Software Defined Radio' Terminals
                 Dieter Greifendorf, Joerg Stammen and Peter Jung;
                 FhG, Germany

05:20 - 05:40pm:  Configurable Systems-on-Chips: Challenges and Perspectives for Industry and Universities
                 Juergen Becker;
                 Univ. of Karlsruhe, Germany

05:40 - 06:00pm: Enabling Hardware-Software Multitasking on a Reconfigurable Computing Platform for Networked Portable Multimedia Appliances
                 J-Y. Mignolety, S. Vernalde, D. Verkest and R. Lauwereins;
                 IMEC, Belgium
 

JUNE 26, 2002 (WEDNESDAY)
 
 

08:20 - 11:00am

SESSION 3-ERSA:   Custom Computing Machines for Image Processing (CCMIP)
                     Chairman: Marek Gorgon, Technical University of St. Staszic, Krakow, Poland
                          (Location: Conference Room F)
 

08:20 - 08:40am:  A Virtual Component for Motion Estimation Algorithm
                 Sebastien Pillement*, Daniel Chillet* and Olivier Sentieys**;
                 *LASTI-ENSSAT-Univ. of Rennes, France;
                 **IRISA-INRIA, France

08:40 - 09:00am:  FPGA Based Vector Quantizer for Bitrate Control in Image Compression
                 Pawel Russek and Kazimierz Wiatr;
                 AGH Tech. Univ. of Cracow, Poland

09:00 - 09:20am:  Different Motion Estimation Processors Architecture Implemented in FPGA Structures for Real-Time Systems
                 Andrzej Ryszko and Kazimierz Wiatr;
                 AGH Tech. Univ. of Cracow, Poland

09:20 - 09:40am:  GOM: A GTM OptimalMapping Tool for Reconfigurable Computers
                 Jack Jean, Xuejun Liang, Xinzhoang Guo, Hua Zhang and Fei Wang;
                 Wright State Univ., USA; Jackson State Univ., USA

09:40 - 10:00am:  ANSI C and Handel-C Based Rapid Prototyping Framework for Real-Time Image Processing Algorithms
                 P. Voles, L. Holasek and M. Vasilko;
                 Bournemouth Univ., UK

10:00 - 10:40am:  B-ERSA: DISCUSSION SESSION + REFRESHMENTS
                 RRR + SRP + Posters (List of papers appears at the end of conference program.)
                (Location: Meeting Rooms: 1 - 5)

SESSION 3-ERSA: (Continued) Custom Computing Machines for Image Processing (CCMIP)
                           (Location: Conference Room F)

10:40 - 11:00am:  Reconfigurable Image Processing Architectures - Research  and Current State of Art at the AGH Technical University
                 Ryszard Tadeusiewicz, Marek Gorgon, Kazimier Wiatr and Zbigniew Mikrut;
                AGH Tech. Univ., Krakow, Poland
 

11:00 - 02:00pm

SESSION 4-ERSA:   Engineering of Configurable Systems  (ECS)
                         Chairman:  Toomas Plaks, SBU, London
                         (Location: Conference Room F)

11:00 - 11:20am:  Effective and Efficient Circuit Synthesis Tools for FPGA-Based Reconfigurable Systems
                 Lech Jozwiak and Aleksander Slusarczyk;
                 Eindhoven Univ. of Technology, The Netherlands

11:20 - 11:40am:  Automatic Generation of Systolic Array Designs For Reconfigurable Computing
                 Greg Nash;
                 Centar, CA, USA

11:40 - 12:00pm:  Memory Access Scheduling and Loop Pipelining
                 Xuejun Liang* and Jack Jean**;
                 *Jackson State Univ., USA;
                 **Wright State Univ., USA

12:00 - 12:20pm:  Pattern Selection: Customized Block Allocation for Domain-Specific Programmable Systems
                 Elaheh Bozorgzadeh, Seda Ogrenci Memik, Ryan Kastner and Majid Sarrafzadeh;
                 Univ. of California, Los Angeles, USA

12:20 - 01:20pm:  LUNCH (On Your Own)

01:20 - 01:40pm:  Domain-Specific Modeling for Rapid System-Level Energy Estimation of Reconfigurable Architectures
                 Seonil Choi, Ju-wook Jang, Sumit Mohanty and Viktor K. Prasanna;
                 Univ. of Southern California, Los Angeles, USA

01:40 - 02:00pm:  Evaluation of Rapid Context Switching on a CSRC Device
                 David I. Lehn, Kiran Puttegowda, Jae H. Park, Peter M. Athanas and Mark T. Jones;
                 Virginia Tech, USA
 

02:00 - 06:00pm

SESSION 5-ERSA: Operating System Approaches for Reconfigurable Hardware (OS)
                         Chairman: Marco Platzner,   ETH, Zurich, Switzerland
                         (Location: Conference Room F)
 

02:00 - 02:20pm:  On Enforced Convergence of ACO and its Implementation on the Reconfigurable Mesh Architecture Using Size Reduction Tasks
                 Stefan Janson*, Daniel Merkle*, Martin Middendorf**, Hossam ElGindy*** and Hartmuck Schmeck*;
                 *Univ. of Karlsruhe, Germany;
                 **Catholoc Univ. of Eichstatt-Ingolstadt, Germany;
                 ***Univ. of New South Wales, Australia

02:20 - 02:40pm:  Research Issues in Operating Systems for Reconfigurable Computing
                 Grant B. Wigley and David A. Kearney;
                 Univ. of South Australia, Australia

02:40 - 03:00pm:  Interface Synthesis for FPGA based VLSI Processor Arrays
                 Marcus Bednara and Juergen Teich;
                 Univ. of Paderborn, Germany

03:00 - 03:20pm:  Non-Preemptive Multitasking on FPGAs: Task Placement and Footprint Transform
                 Herbert Walder and Marco Platzner;
                 Swiss Federal Institute of Technology (ETH), Switzerland

03:20 - 03:40pm: BREAK

03:40 - 04:00pm:  A Framework for Automatic Generation of Configuration Files for a Custom Hardware/Software RTOS
                 Jaehwan Lee, Kyeong Keol Ryu and Vincent John Mooney III;
                 Georgia Institute of Technology, USA

04:00 - 04:20pm:  Design Techniques to Implement Reconfigurable Hardware Watch-Points for Hardware/Software Co-Debugging
                 Karen Tomko and Anurag Tiwari;
                 Univ. of Cincinnati, USA
 
 

DISCUSSION SESSIONS
 

JUNE 24 (MONDAY), 2002
 
 

A-ERSA:

 10:45 - 11:45am
(Location: Meeting Rooms: 1 - 5)
 

1.   Scheduling though Simulation Optimization using Iterative Improvement

Alex Cave, Saeid Nahavandi and Abbas Kouzani;
Deakin Univ., Australia
 
2. Using Bottlenecks to Control Production Inventory

Bruce Gunn and Saeid Nahavandi;
Deakin Univ., Australia
 
3.  Evaluating Task Redistribution Methods for Fault Clearing in Multi-Agent Systems

Maryam S. Mirian, Majid Nili Ahmadabadi and Zainalabedin Navabi;
University of Tehran, Iran
 

JUNE 26 (WEDNESDAY), 2002
 

B-ERSA

10:00 - 10:40am
(Location: Meeting Rooms: 1 - 5)
 
 

1. Research on Rapid Reconfigurable Information System and  its Key Technologies

Ding Qiulin and Shen Yansen; Nanjing
Univ. of Aeronautics & Astronautics, P. R. China
 
2. Implementing an MP3 Decoder on Reconfigurable Hardware

Grant B. Wigley, John P. Hopf and David A. Kearney;
Univ. of South Australia, Australia
 
3. Efficient Allocation of FPGA Area to Multiple Users in an Operating System for Reconffigurable Computing

Martyn A. George, Matthew Pink, David A. Kearney and Grant B. Wigley;
Univ. of South Australia, Australia
 
4. Field Programmable Technology Implementation of Target Recognition Using Geometric Hashing

David Warren, David A. Kearney and Grant B. Wigley;
Univ. of South Australia, Australia